Inter-Core Synchronization

WAIT

WAIT rd

• Performs instruction synchronization between dual processing cores, where the ID of the target processing core to be synchronized is specified by GRF[rd].

Example:

WAIT $1

BARRIER

BARRIER rs,rt

Performs instruction synchronization across multiple processing cores

• The number of processing cores is specified by GRF[rs];
• The barrier ID is specified by GRF[rt], uniquely identifying the current synchronization operation and used for acknowledgment by the participating processing cores.

Example:

BARRIER $1,$2