Instruction Design

Instruction Overview

To support efficient execution across the hardware hierarchy, CIMFlow implements a unified 32-bit instruction format with specialized variations for different operation types.

Instructions are categorized into compute, communication, and control flow instructions, with compute instructions further specialized for CIM, vector, and scalar compute units.

• Basic Structure: Each instruction contains a 6-bit operation specifier (opcode) and multiple 5-bit operand fields.
• Supplementary Fields: Certain instruction types may also include supplementary fields, such as a 6-bit functionality specifier, execution flags, or immediate values of 10 or 16 bits.
• Flexibility and Efficiency: The instruction format supports up to four operands depending on the operation type, providing flexibility for complex operations while maintaining encoding efficiency.

The instruction set is designed for extensibility through incorporating a customized instruction description template, which enables seamless integration of new operations into the framework when provided with their associated performance parameters.

Register Overview

General-Purpose Registers

The ISA defines 32 general-purpose registers, encoded with 5-bit addresses, suitable for standard computational tasks.

Special-Purpose Registers

There are 32 special-purpose registers that can be grouped

• CIM Unit Registers (IDs 0-15): These registers are used specifically by the CIM unit to handle parameters such as input/output bit widths, group sizes, and other CIM-related configurations.
• Vector Unit Registers (IDs 16-31): These registers are dedicated to VEC_OP operations, such as specifying input vector parameters and addressing for multiple input vectors.

Detailed

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