Instruction Set ArchitectureInstruction Design
Special-Purpose Registers
CIM Unit Registers (IDs 0-15)
| ID | Register Name | Description |
|---|---|---|
| 0 | CIM_IBW | Specifies the bit width of input data. |
| 1 | CIM_OBW | Specifies the bit width of output data. |
| 2 | CIM_WBW | Specifies the bit width of weights. |
| 3 | CIM_GSZ | Defines the size of Macro Groups, indicating the number of Macros per Group. Must adhere to values specified in the configuration file. |
| 4 | CIM_AG | Number of active Groups in the CIM unit. |
| 5 | CIM_AE | Number of active Elements per column in each Group. |
| 6 | CIM_GSTEP | Offset address for each group's input vector, defined as the step size relative to the previous group or an offset from the address in register rs1. |
| 7 | CIM_VMASK | Starting address for the sparse mask for value-level sparsity. |
| 8 | CIM_BMETA | Starting address for bit-level sparse metadata. |
| 9-15 | RESERVED | Reserved for future extensions. |
Vector Unit Registers (IDs 16-31)
| ID | Register Name | Description |
|---|---|---|
| 16 | VEC_IBW1 | Bit width for each element of Input Vector 1. |
| 17 | VEC_IBW2 | Bit width for each element of Input Vector 2. |
| 18 | VEC_IBW3 | Bit width for each element of Input Vector 3. |
| 19 | VEC_IBW4 | Bit width for each element of Input Vector 4. |
| 20 | VEC_OBW | Bit width for each element of the output vector. |
| 21 | VEC_IA3 | Starting address for Input Vector 3. |
| 22 | VEC_IA4 | Starting address for Input Vector 4. |
| 23-31 | RESERVED | Reserved for additional instructions or future extensions. |
Special-to-General Register Binding
To optimize register utilization, specific special-purpose registers can be bound to general-purpose registers during configuration.
This binding reduces the overhead of frequent assignments and allows registers to serve multiple purposes during different phases of execution.
Binding Configuration Example:
[
{
"special": 7,
"general": 30
},
{
"special": 8,
"general": 31
}
]In the above configuration,
special-purpose register 7 (CIM_VMASK) is bound to general-purpose register 30,
and register 8 (CIM_BMETA) is bound to general-purpose register 31.