Simulator

The Simulator section documents CIMFlow-Simulator, the SystemC-based cycle-accurate simulator that executes ISA instruction streams produced by the CIMFlow compiler and produces cycle/energy reports.

Scope

This section covers:

Cycle-level execution model (Chip → Core → Units hierarchy)
Memory hierarchy, NoC transfer, and synchronization semantics
Input file formats and validation rules
CLI interfaces and output metrics

Boundary with Other Sections

For ISA definitions see Abstraction, for compilation see Compiler, for end-to-end workflow see Framework.

Page Map

Run and CLI

cimflow sim and native cim-simulator commands, options, and return codes.

Architecture

Chip/Core/Unit composition and module boundaries.

Execution and Resource Model

Decode-issue lifecycle, conflicts, and control semantics.

Memory, Network and Transfer

Address-space mapping, transfer paths, and NoC cost model.

Input Files

Required JSON structures and validation rules.

Output and Metrics

Output formats and performance metric definitions.

Code Coverage Map

The tree below shows the source directory layout of the CIMFlow-Simulator C++ codebase. For a detailed file-level view, see Architecture / Source Directory Map.