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Compiler

Two-level compiler stack from ONNX graph partitioning to CIM ISA generation

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The Compiler section documents CIMFlow-Compiler, the compiler that converts ONNX neural network models into ISA instruction streams for the CIMFlow simulator.

Scope

This section covers:

  • Two-level compilation flow (CG-level graph partitioning and OP-level ISA generation)
  • MLIR-based DSL backend for operator kernel code generation
  • Configuration formats and hardware parameter constraints
  • Command-line reference for cim-compiler commands

Boundary with Framework and Simulator

This section focuses on compiler internals and interfaces. End-to-end workflow usage is documented in Framework, and runtime execution semantics are documented in Simulator.

Page Map

Run and CLI

cim-compiler commands, options, and advanced developer tools.

Pipeline Overview

End-to-end compilation stages and output file formats.

CG-Level

Graph partitioning, stage formation, and CG instruction generation.

OP-Level

Lower CG instructions to ISA with synchronization and per-core emission.

DSL and MLIR Backend

DSL frontend, AST-to-MLIR lowering, pass pipeline, and code generation.

Configuration and Constraints

Config formats, parameter checks, and compatibility rules.

Code Coverage Map

The tree below shows the source directory layout of the CIMFlow-Compiler Python package.

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Run and CLI

Command reference for CIMFlow compiler commands and native cim-compiler tools

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Scope
Page Map
Code Coverage Map