Input Files
Configuration, instruction, and network file formats and validation rules
The simulator requires three JSON files to run: a hardware configuration that defines the chip architecture, an instruction file with per-core ISA streams, and a network matrix that defines NoC latency and energy costs.
Input Files Overview
Each file maps to a CLI argument:
| File | CLI Argument | Required | Error on Invalid |
|---|---|---|---|
| Hardware/simulation config | Positional <config> | Yes | INVALID_CONFIG |
| Instruction file | Positional <inst> | Yes | INVALID_INSTRUCTION_FILE |
| NoC matrix JSON | Referenced inside config | Yes | NETWORK_CONFIG_NOT_FOUND |
Failure Codes
Return-code details are listed in Run and CLI.
Hardware and Simulation Config
Top-level skeleton:
{
"chip_config": {
"core_cnt": 1,
"core_config": { "...": "..." },
"global_memory_config": { "...": "..." },
"network_config": {
"bus_width_byte": 16,
"network_config_file_path": "./network/flit16dim8.json"
},
"address_space_config": [
{ "name": "cim_unit", "size": 1024 }
]
},
"sim_config": {
"period_ns": 1.0,
"sim_mode": "run_one_round",
"data_mode": "real_data"
}
}Path Resolution
All embedded paths — the NoC matrix (network_config_file_path), local memory images, and global memory images — are resolved relative to the config file's directory, not the working directory.
Instruction File
Expected structure is per-core arrays keyed by numeric string core IDs.
{
"metadata": {
"op_count": 123456789
},
"0": [
{ "opcode": 44, "rd": 1, "imm": 1024 },
{ "opcode": 48, "rs": 1, "rt": 2, "rd": 3, "imm": 0 }
],
"1": [
{ "opcode": 44, "rd": 4, "imm": 0 }
]
}Network Latency/Energy Matrix
The network_config_file_path field points to a matrix file defining NoC costs.
{
"latency": {
"0": { "1": 3, "2": 4 },
"1": { "0": 3 }
},
"energy": {
"0": { "1": 1.2, "2": 1.6 },
"1": { "0": 1.2 }
}
}latency[src][dst]: Per-flit latency in cyclesenergy[src][dst]: Per-flit dynamic energy in pJ- Flit count per transaction:
ceil(data_size / bus_width_byte)
Pre-Simulation Checklist
Before running simulation:
- Ensure
core_cntmatches instruction core entries (0..core_cnt-1) - Verify memory names are unique and address-space mapping is one-to-one
- Confirm the NoC matrix path exists and is readable
- Check that memory image files exist when configured
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